The present invention relates to a signal input circuit, and more particularly to an input circuit of a type in which an input signal is compared with a reference voltage to detect a logic level of the input signal.
A signal input circuit of this type is widely employed in, for example, a semiconductor memory as an address input circuit and a data input circuit. It comprises a flip-flop circuit, a first transistor supplied with an input signal and connected between a first input terminal of the flip-flop circuit and a reference terminal, and a second transistor supplied with the reference voltage and connected between a second input terminal of the flip-flop circuit and the reference terminal.
When the level of the input signal is larger than the reference voltage, the first transistor takes an internal resistance smaller than the second transistor, so that the first input terminal takes the low level. When the input signal takes the low level or a level that is smaller than the reference voltage, the first transistor is turned OFF or has a high internal resistance. As a result, the second input terminal takes the low level. The second transistor is in the conductive state regardless of whether or not the level of the input signal is larger than the reference voltage, and therefore a d.c. current flows between power supply terminals through the second transistor and an internal load of the flip-flop circuit. The power consumption is thereby increased. Moreover, the potential at the second input terminal is determined by the resistance ratio between the second transistor and the internal load of the flip-flop circuit when the input signal takes the level higher than the reference voltage. In other words, the second input terminal assumes an intermediate level between the high level and the low level. For this reason, the potential difference between the first and second input terminals is not amplified sufficiently only by an output amplifier, so that another flip-flop circuit is required to produce and hold the high level and low level output signals. The circuit construction is thereby made complicated. Furthermore, if the level of the input signal varies after one of the first and second input terminals takes the low level, the potentials at the other input terminal is changed. In order to avoid this defect, the signal input circuit further includes first and second gates. The input signal is supplied through the first gate to the first transistor, and the reference voltage is supplied via the second gate to the second transistor. The first and second gates are opened by a clock signal only during a predetermined time period. This means that the circuit construction is further made complicated.